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w83194r - 58a 100mhz agp clock for via chipset publication release date: nov. 1999 - 1 - revision 0.30 1.0 general descrip tion the w83194r - 58a is a clock synthesizer for via chipset. w83194r - 58a provides all clocks required for high - speed risc or cisc microprocessor such as intel pentiumii and also provides 16 different frequencies of cpu clocks by softwa re setting. agp and pci clocks are externally selectable with smooth transitions. the w83194r - 58a provides agp clocks especially for clone chipset, and makes sdram in synchronous frequency with cpu or agp clocks. the w83194r - 58a provides i 2 c serial bus interface to program the registers to enable or disable each clock outputs and choose the 0.25%, 0.5% or 0.5%,1.5% center type spread spectrum to reduce emi. the w83194r - 58a accepts a 14.318 mhz reference crystal as its input and runs on a 3.3v suppl y. high drive pci and sdram clock outputs typically provide greater than 1 v /ns slew rate into 30 pf loads. cpu clock outputs typically provide better than 1 v /ns slew rate into 20 pf loads when maintaining 50 5% duty cycle. the fixed frequency outputs as ref, 24mhz, and 48 mhz provide better than 0.5v /ns slew rate. 2.0 product feature s supports pentium ? , pentium ? pro, pentium ? ii, amd and cyrix cpus with i 2 c. 4 cpu clocks 12 sdram clocks for 3 dims two agp clocks 6 pci synchronous clocks. op tional single or mixed supply: (vdd = vddq3 = vddq2 = vddq2b = 3.3v) or (vdd = vddq3 = vddq2 = 3.3v, vdq2b = 2.5v) skew form cpu to pci clock - 1 to 4 ns, center 2.6 ns, agp to cpu sync. skew 0 ns (250 ps) sdram frequency synchronous to cpu or agp clocks smooth frequency switch with selections from 60 to 100 mhz cpu( - 37) and 66 to 150mhz( - 58) i 2 c 2 - wire serial interface and i 2 c read back 0~ 0.5% down type and 0.25%, 0.5% center type spread spectrum to reduce emi programmable registers to enable/sto p each output and select modes (mode as tri - state or normal ) mode pin for power management 48 mhz for usb 24 mhz for super i/o 48 - pin ssop package
w83194r - 58a preliminary publication release date: nov. 1999 - 2 - revision 0.30 3.0 block diagram pll2 xtal osc spread spectrum pll1 latch por stop ? 2 control logic config. reg. stop stop pci clock divder ~ ~ 5 2 12 3 5 48mhz 24mhz ref(0:1 ) agp(0:1) cpuclk(0:3) sdram(0:11) pciclk(0:4) pciclk_f x1 x2 *fs(0:2) 3 *mode cpu_stop# pci_stop# *sdata *sclk 2 4 cpu3.3#_2.5 cpu_stop# pci_stop# *sd_sel# 4.0 pin configurati on
w83194r - 58a preliminary publication release date: nov. 1999 - 3 - revision 0.30 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 vdd * ref0/cpu3.3#_2.5 vss xin xout vddq3 pciclk_f/*fs1 pciclk0/*fs2 vss pciclk1 pciclk2 pciclk3 pciclk4 vddq3 agp0 vss cpu_stop#/sdram11 pci_stop#/sdram10 vddq3 sdram 9 sdram 8 vss sdata sdclk vddq2 agp1 ref1/*sd_sel# vss cpuclk0 cpuclk1 vddq2b cpuclk2 cpuclk3 vss sdram 0 sdram 1 sdram 2 vddq3 sdram 3 vss sdram 4 sdram 5 sdram 6 sdram 7 vss vddq3 48mhz/*fs0 24mhz/*mode 5.0 pin description in - input out - output i/o - bi - directional pin # - active low * - internal 250k w pull - up 5.1 crystal i/o symbol pin i/o function xin 4 in crystal input with internal loading capacitors and feedback resistors. xout 5 out crystal output at 14.318mhz nominally. 5.2 cpu, sdram, pci clock outputs symbol pin i/o function cpuclk [ 0:3 ] 40,41,43,44 out low skew (< 250ps) clock outputs for host frequencies such as cpu, chipset and cache. vddq2b is the supply voltage for these outputs.
w83194r - 58a preliminary publication release date: nov. 1999 - 4 - revision 0.30 agp[ 0:1] 15,47 out accelerate graphic port clock outputs sdram11/ cpu_stop# 17 i/o if mode =1 (default), then this pin is a sdram clock buffered output of the crystal. if mode = 0 , then this pin is cpu_stop# input used in power mana gement mode for synchronously stopping the all cpu clocks. sdram10/ pci_stop# 18 i/o if mode = 1 (default), then this pin is a sdram clock output. if mode = 0 , then this pin is pci_stop # and used in power management mode for synchronously stopping the all pci clocks. sdram [ 0:9] 20,21,28,29,31 ,32,34, 35,37,38 o sdram clock outputs which have the same frequency as cpu clocks. pciclk_f/ *fs1 7 i/o latched input for fs1 at initial power up for h/w selecting the output frequency of cpu, sdram and pci clo cks. free running pci clock during normal operation.
w83194r - 58a preliminary publication release date: nov. 1999 - 5 - revision 0.30 5.2 cpu, sdram, pci clock outputs, continued symbol pin i/o function pciclk 0 / *fs2 8 i/o latched input for fs2 at initial power up for h/w selecting the output frequency of cpu, sdram and pci clocks. pci clock during normal operation. pciclk [ 1:4 ] 10,11,12,13 out low skew (< 250ps) pci clock outputs. 5.3 i 2 c control interface symbol pin i/o function sdata 23 i/o serial data of i 2 c 2 - wire control interface sdclk 24 in serial clock of i 2 c 2 - wi re control interface 5.4 fixed frequency outputs symbol pin i/o function ref0 / cpu3.3#_2.5 2 i/o internal 250k w pull - up. latched input for cpu3.3#_2.5 at initial power up. reference clock during normal operation. latched high - vddq2b = 2.5v latched low - vddq2b = 3.3v ref1 /*sd_sel# 46 i/o internal 250k w pull - up. latched input at power on selects either cpu(sdsel=1) or agp(sd_sel=0) frequencies for sdram clock outputs. 24mhz / *mode 25 i/o internal 250k w pull - up. latched input for mode at initial power up. 24mhz output for super i/o during normal operation. 48mhz / *fs0 26 i/o internal 250k w pull - up. latched input for fs0 at initial power up for h/w selecting the output frequency of cpu, sdram and pci clocks. 48mhz output for usb during normal operation.
w83194r - 58a preliminary publication release date: nov. 1999 - 6 - revision 0.30 5.5 power pins symbol pin function vdd 1 power supply for ref [0:1] crystal and core logic. vddq2 42 power supply for agp1 and ref1 output, either 2.5v or 3.3v. vddq2b 48 power supply for cpuclk[0:3], either 2.5v or 3.3v. vddq3 6,14,19, 30, 36 power supply for sdram, pciclk and 48/24mhz outputs. vss 3,9,16,22,27, 33,39,45 circuit ground. 6.0 frequency selec tion by hardware 6.2 w83194r - 58 frequency selection table fs2 fs1 fs0 cpu(mhz) sdram (mhz) pci (mhz) agp (mhz) ref (mhz) sd_sel=1 sd_sel=0 0 0 0 112 112 74.7 37.3 74.7 14.318 0 0 1 66.8 66.8 66.8 33.4 66.8 14.318 0 1 0 97.0 97.0 64.67 32.33 64.67 14.318 0 1 1 75 75 75 37.5 75 14.318 1 0 0 133.3 133.3 88.7 44.3 88.7 14.318 1 0 1 83.3 83.3 66.6 33.3 66.6 14.318 1 1 0 95.25 95.25 63.5 31.75 63.5 14.318 1 1 1 100.2 100.2 66.8 33.4 66.8 14.318 7.0 cpu 3.3#_2.5 bu ffer selection cpu 3.3#_2.5 ( pin 2 ) input level cpu operate at 1 vdd = 2.5v 0 vdd = 3.3v
w83194r - 58a preliminary publication release date: nov. 1999 - 7 - revision 0.30 8.3 serial control registers the pin column lists the affected pin number and the @powerup column gives the state at true power up. registers are set to the values shown only on true power up. "command code" byte and "byte count" byte must be sent following the acknowledge of the address byte. although th e data (bits) in these two bytes are considered "don't care", they must be sent and will be acknowledge. after that, the below described sequence (register 0, register 1, register 2, ....) will be valid and acknowledged. 8.3.1 register 0: cpu frequency select register bit @powerup pin description 7 0 - 0 = 0.25% spread spectrum modulation 1 = 0.5% spread spectrum modulation(w83194r - 58) 6 0 - ssel2 ( frequency table selection by software via i 2 c) 5 0 - ssel1 ( frequency table selection by software via i 2 c) 4 0 - ssel0 ( frequency table selection by software via i 2 c) 3 0 - 0 = selection by hardware 1 = selection by software i 2 c - bit 6:4 2 0 - ssel3 (frequency table selection by software via i 2 c for w83194r - 58) 1 0 - 0 = normal 1 = spread spectrum enabled 0 0 - 0 = running 1 = tristate all outputs
w83194r - 58a preliminary publication release date: nov. 1999 - 8 - revision 0.30 w83194r - 58 frequency table selection by software via i 2 c ssel2 ssel1 ssel0 register0 bit2 cpu (mhz) sdram (mhz) pci (mhz) agp (mhz) ref (mhz) ssel3 sd_sel=1 sd_sel=0 0 0 0 0 112 112 74. 7 37.3 74.7 14.318 0 0 1 0 66.8 66.8 66.8 33.4 66.8 14.318 0 1 0 0 97.0 97.0 64.67 32.33 64.67 14.318 0 1 1 0 75 75 75 37.5 75 14.318 1 0 0 0 133.3 133.3 88.7 44..3 88.7 14.318 1 0 1 0 83.3 83.3 66.6 33.3 66.6 14.318 1 1 0 0 95.25 95.25 63.5 31.75 63.5 14.318 1 1 1 0 100.2 100.2 66.8 33.4 66.8 14.318 0 0 0 1 103 103 68.7 34.3 68.7 14.318 0 0 1 1 112 112 74.7 37.3 74.7 14.318 0 1 0 1 115 115 76.6 38.3 76.6 14.318 0 1 1 1 120 120 80 40 80 14.318 1 0 0 1 124 124 82 31 62 14.318 1 0 1 1 133.3 133.3 66.6 33.3 66.6 14.318 1 1 0 1 140 140 70 35 70 14.318 1 1 1 1 150 150 75 37.5 75 14.318 function table function outputs description cpu pci sdram ref ioapic tri - state hi - z hi - z hi - z hi - z hi - z normal see table see table cpu 14.318 14.318
w83194r - 58a preliminary publication release date: nov. 1999 - 9 - revision 0.30 8.3.2 register 1 : cpu , 48/24 mhz clock register (1 = active, 0 = inactive) bit @powerup pin description 7 1 - 0 = 0.5% down type spread, overrides byte0 - bit7. 1= center type spread. 6 1 - reserved 5 1 - reserved 4 1 - reserved 3 1 40 cpuclk3 (active / i nactive) 2 1 41 cpuclk2 (active / inactive) 1 1 43 cpuclk1 (active / inactive) 0 1 44 cpuclk0 (active / inactive) 8.3.3 register 2: pci clock register (1 = active, 0 = inactive) bit @powerup pin description 7 x - reserved 6 1 7 pciclk_f (active / inactive) 5 1 15 agp0 (active / inactive) 4 1 14 pciclk4 (active / inactive) 3 1 12 pciclk3 (active / inactive) 2 1 11 pciclk2 (active / inactive) 1 1 10 pciclk1 (active / inactive) 0 1 8 pciclk0 (active / inactive)
w83194r - 58a preliminary publication release date: nov. 1999 - 10 - revision 0.30 8.3.4 register 3: sdram clock register (1 = active, 0 = inactive) bit @powerup pin description 7 1 28 sdram7 (active / inactive) 6 1 29 sdram6 (active / inactive) 5 1 31 sdram5 (active / inactive) 4 1 32 sdram4 (active / inactive) 3 1 34 sdram3 (active / inactive) 2 1 35 sdram2 (active / inactive) 1 1 37 sdram1 (active / inactive) 0 1 38 sdram0 (active / inactive) 8.3.5 register 4: additional sdram clock register (1 = active, 0 = inactive) bit @powerup pin description 7 x - reserved 6 x - reserved 5 x - reserved 4 x - rese rved 3 1 17 sdram11 (active / inactive) 2 1 18 sdram10 (active / inactive) 1 1 20 sdram9 (active / inactive) 0 1 21 sdram8 (active / inactive) 8.3.6 register 5: peripheral control (1 = active, 0 = inactive) bit @powerup pin description 7 x - reserved 6 x - reserved 5 x - reserved 4 1 47 agp1 (active / inactive) 3 x - reserved 2 x - reserved 1 1 46 ref1 (active / inactive) 0 1 2 ref0 (active / inactive)
w83194r - 58a preliminary publication release date: nov. 1999 - 11 - revision 0.30 8.3.7 register 6: reserved register bit @powerup pin description 7 x - reserved 6 x - reserved 5 x - reserved 4 x - reserved 3 x - reserved 2 x - reserved 1 x - reserved 0 x - reserved 9 .0 ordering informa tion part number package type production flow w83194r - 58 a 48 pin ssop commercial, 0 c to +70 c 10 .0 how to read the top marking 1st line: winbond logo and the type number: w83194r - 58 a 2nd line: tracking code 2 8051234 2 : wafers manufactured in winbond fab 2 8051234 : wafer production series lot number 3rd line: tracking code 814 g b b 814 : packages made in ' 98 , week 14 g : assembly house id; a means ase, s means spil, g means gr bb : ic revision all the trade marks of products and companies mentioned in this data sheet belong to their respective owners . w83194r - 58a 28051234 814gb b
w83194r - 58a preliminary publication release date: nov. 1999 - 12 - revision 0.30 11 .0 package drawing and dimensions headquarters no. 4, creation rd. iii science-based industrial park hsinchu, taiwan tel: 886-35-770066 fax: 886-35-789467 www: http://www.winbond.com.tw/ taipei office 11f, no. 115, sec. 3, min-sheng east rd. taipei, taiwan tel: 886-2-7190505 fax: 886-2-7197502 tlx: 16485 wintpe winbond electronics (h.k.) ltd. rm. 803, world trade square, tower ii 123 hoi bun rd., kwun tong kowloon, hong kong tel: 852-27516023-7 fax: 852-27552064 winbond electronics (north america) corp. 2730 orchard parkway san jose, ca 95134 u.s.a. tel: 1-408-9436666 fax: 1-408-9436668 please note that all data and specifications are subject to change without notice. all the trade marks of products and c ompanies mentioned in this data sheet belong to their respective owners . these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify winbond for any damages resulting from such improper use or sale.
w83194r - 58a preliminary publication release date: nov. 1999 - 13 - revision 0.30

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